Arduino MKR Vidor 4000 FPGA Guide: Quartus, Bitstreams, HDMI, Camera and Custom Logic

The Arduino MKR Vidor 4000 is one of the most unusual Arduino boards ever released because it combines a conventional microcontroller with a real FPGA.

The board contains:

The key idea is that the FPGA is not simply a faster processor.

It allows you to build custom digital hardware that runs in parallel with the SAMD21.

Current Product Status

Arduino now marks the:

as:

That does not make the board useless.

It remains interesting for:

• existing installations;
• FPGA learning;
• video experiments;
• custom digital interfaces;
• high-speed signal processing.

But new production designs should consider long-term availability.

FPGA Hardware Resources

The Cyclone 10CL016 provides approximately:

plus:

for FPGA applications.

Arduino states that around:

of the FPGA QSPI Flash is allocated for user FPGA applications.

FPGA Clocking

The board provides a base:

clock to the FPGA system.

The FPGA can use internal PLLs to generate higher-frequency clocks, and Arduino documents FPGA operation up to approximately:

depending on the design.

High-Speed I/O

Arduino states that FPGA pins can toggle at:

under suitable timing and configuration.

That makes the FPGA useful for tasks that are awkward to implement with:

Why an FPGA Is Different from a Microcontroller

A microcontroller normally executes instructions sequentially:

An FPGA can implement multiple hardware blocks simultaneously:

all operating in parallel.

Two Levels of FPGA Development

There are two broad ways to use the FPGA on Vidor.

1. Arduino Libraries with Prebuilt FPGA Images

Arduino libraries can load a prebuilt FPGA configuration and expose functions to the SAMD21 sketch.

This is the easiest path.

The sketch behaves like:

2. Custom Quartus FPGA Development

The advanced path uses:

to design your own FPGA logic.

This means working with:

• Verilog or VHDL;
• block diagrams;
• pin constraints;
• clock constraints;
• synthesis;
• place and route;
• timing analysis;
• bitstream generation.

Arduino’s Historical Vidor FPGA Toolchain

Arduino’s Vidor FPGA repositories were built around:

with project templates and helper scripts.

The archived Vidor repositories include examples for:

• graphics;
• peripherals;
• mailbox/RPC communication;
• bare custom FPGA projects.

The Official FPGA Repository Is Archived

The:

repository is now archived and read-only.

This fits the board’s current EOL status.

For existing projects, that repository remains valuable documentation of the original FPGA workflow.

Typical Custom FPGA Workflow

A simplified workflow is:

The FPGA Is Normally Configured by the SAMD21

Vidor’s normal Arduino-oriented architecture uses the SAMD21 to load the FPGA image.

The FPGA does not simply run an independent Arduino sketch.

A typical startup becomes:

Bitstream Packaging

Quartus generates FPGA configuration data, but Arduino’s original Vidor workflow required additional processing before the image could be embedded into an Arduino project.

Historical tools converted the Quartus output into a format that could be included as something conceptually like:

and transferred to the FPGA by the SAMD21.

Why the Bitstream Is Not Just an Arduino Binary

The SAMD21 and Cyclone FPGA use completely different programming models.

The SAMD21 receives:

while the FPGA receives:

describing the digital hardware structure.

SAMD21-to-FPGA Communication

Once custom logic is running, you need a way for the SAMD21 sketch to exchange data with it.

Possible approaches include:

• memory-mapped register schemes;
• mailbox/RPC interfaces;
• JTAG-based interfaces;
• SPI-like custom links;
• shared GPIO/control registers.

This interface must be designed deliberately.

Prebuilt Libraries Hide the Communication Layer

When using an Arduino-provided Vidor library, it may appear that your sketch simply calls:

and the hardware reacts.

Behind that call is a communication protocol between the SAMD21 and FPGA.

When creating your own bitstream, you need to recreate or replace that communication mechanism.

Mailbox / RPC Template

The archived Vidor bitstream projects include a:

project designed around Arduino’s soft-core mailbox/RPC-style mechanism.

This is useful when the SAMD21 needs to:

• write control registers;
• read counters;
• configure FPGA blocks;
• exchange status information.

Bare FPGA Template

The:

project is intended for users who want to build their own communication architecture.

That gives maximum freedom, but also means the application must define how the SAMD21 and FPGA exchange commands and data.

Shared MKR Pins

Arduino’s current datasheet states that all normal board header pins are driven/routed so both the:

can access the MKR-format signals.

This is powerful but also dangerous if both devices drive the same line.

Shared-Pin Ownership Rule

Use this rule:

For example:

Configure the unused side as:

where appropriate.

Electrical Contention

If the SAMD21 outputs HIGH while the FPGA outputs LOW on the same net:

the devices fight electrically.

This can cause:

• excess current;
• incorrect logic;
• overheating;
• possible hardware damage.

3.3 V Logic

The Vidor board is a:

logic system.

Do not connect 5 V signals directly to FPGA or SAMD21 I/O unless the exact circuit is explicitly verified.

FPGA I/O Drive Strength

The official datasheet lists FPGA I/O current options around:

depending on I/O standard and configuration.

This is logic-level drive, not load power.

Use external buffers or drivers for:

• relays;
• motors;
• large LED arrays;
• long cables;
• high-current loads.

FPGA Soft Peripherals

One of the board’s most interesting capabilities is creating extra peripherals in FPGA logic.

Arduino documents configurations with up to:

depending on FPGA configuration.

This Is Not a Fixed Hardware Count

The Cyclone FPGA does not contain seven permanently wired UART blocks.

Instead:

according to the loaded design.

Using more peripherals consumes FPGA logic and routing resources.

Custom PWM

FPGA PWM can be far more flexible than SAMD21 PWM.

You can create:

• many independent channels;
• custom frequencies;
• very high resolution;
• phase-aligned channels;
• centre-aligned PWM;
• precise dead-time generation.

High-Speed Counter Example

A frequency counter implemented in SAMD21 software might need:

• interrupts;
• timer capture;
• careful latency management.

An FPGA implementation can simply count incoming edges in hardware:

with deterministic timing.

Quadrature Encoder Example

The FPGA can decode multiple encoder channels simultaneously:

This removes interrupt load from the Cortex-M0+.

Micro HDMI Output

The Vidor includes:

connected to the FPGA subsystem.

This is one of the clearest demonstrations of why FPGA hardware matters.

Video timing requires precise parallel generation of:

• pixel clocks;
• horizontal timing;
• vertical timing;
• pixel data;
• high-speed serialised signals.

Graphics FPGA Project

The archived Vidor bitstream repository includes a:

project corresponding to the Vidor graphics functionality.

This demonstrates how the FPGA can generate video while the SAMD21 sends higher-level drawing commands.

8 MB SDRAM for Video

Vidor includes:

to support FPGA workloads such as:

• framebuffers;
• image buffers;
• video processing;
• audio buffers;
• large streaming pipelines.

This memory is not normal SAMD21 RAM.

Why 8 MB Matters

For example, an:

requires approximately:

which is far larger than the SAMD21’s:

but practical inside the FPGA SDRAM subsystem.

MIPI Camera Connector

The board also includes a:

connected to the FPGA.

This enables architectures such as:

Camera Workloads Are Naturally Parallel

Image pipelines often involve operations such as:

• pixel capture;
• colour conversion;
• thresholding;
• filtering;
• edge detection;
• scaling;
• framebuffer writing.

FPGA logic can pipeline these operations so different pixels are processed simultaneously at different stages.

QR-Code Demonstrations

Arduino historically demonstrated Vidor camera/FPGA use for:

which is a good example of:

Mini PCIe-Form-Factor Connector

Vidor also exposes:

on a Mini PCI Express-style connector.

This adds a large amount of high-density I/O beyond the standard MKR header.

It Is Not Automatically PCI Express

The connector uses the mechanical Mini PCIe format.

That does not mean:

is automatically implemented.

Any custom high-speed protocol still requires suitable FPGA logic and electrical compatibility.

Timing Constraints Matter

A custom FPGA design is not complete just because it synthesises successfully.

You must define and check:

• clock frequency;
• input timing;
• output timing;
• false paths;
• clock-domain crossings;
• setup/hold timing.

Timing Closure

Quartus timing analysis determines whether the design can reliably run at the requested clock frequency.

If the report says a 200 MHz path fails timing, the design is not guaranteed to operate correctly at 200 MHz simply because simulation looks correct.

Clock-Domain Crossings

A design may have:

Signals crossing between those domains need:

• synchronisers;
• FIFOs;
• handshake logic;
• proper CDC design.

Metastability

An asynchronous external input should not normally be fed straight into arbitrary FPGA logic.

For single-bit signals, use synchroniser flip-flops.

For multi-bit data, use an appropriate:

• FIFO;
• strobe protocol;
• Gray-code counter;
• handshake scheme.

Simulation Before Hardware

FPGA bugs can be difficult to diagnose with:

alone.

A better workflow includes:

• testbench simulation;
• known input vectors;
• timing checks;
• internal logic analyser where available;
• small incremental hardware tests.

SignalTap

Intel Quartus provides:

for internal logic analysis on supported FPGA workflows.

It can capture internal FPGA signals without routing every debug signal to external pins.

JTAG Development

The Vidor FPGA can also be accessed through JTAG-oriented workflows.

Arduino’s archived documentation warns that direct FPGA JTAG access can conflict with the SAMD21 if both attempt to control the FPGA interface.

Keep the SAMD21 in an appropriate state when using an external JTAG programmer.

Start with a Minimal Custom Design

A sensible first custom FPGA project is:

or:

before attempting:

• HDMI;
• camera capture;
• SDRAM controller changes;
• complex multi-clock DSP.

Example FPGA Counter Architecture

This simple example demonstrates the main FPGA advantage:

Example Multi-UART Architecture

An industrial interface could implement:

rather than trying to software-emulate multiple serial ports on a 48 MHz Cortex-M0+.

Example Encoder + PWM Controller

A motor-control support subsystem could contain:

inside the FPGA.

The SAMD21 then handles:

• configuration;
• high-level state machine;
• USB;
• Wi-Fi;
• user interface.

Keep the FPGA for Deterministic Hardware Tasks

A useful division of labour is:

Do Not Put Everything in the FPGA

Tasks such as:

• JSON parsing;
• HTTP;
• Wi-Fi configuration;
• menu logic;
• text processing;

are much easier on the SAMD21 or another processor.

Use FPGA resources where hardware parallelism gives a real advantage.

Resource Usage Matters

Every custom block consumes:

• logic elements;
• registers;
• embedded RAM;
• DSP blocks;
• routing;
• clock resources.

Quartus reports show how much of the Cyclone 10 is used.

FPGA DSP Blocks

The:

are valuable for:

• FIR filters;
• audio processing;
• image filters;
• matrix operations;
• control algorithms.

Using DSP blocks avoids implementing large multipliers from general-purpose logic elements.

FPGA Embedded RAM

The:

is useful for:

• FIFOs;
• lookup tables;
• line buffers;
• packet buffers;
• small frame regions.

Common Mistake 1: Thinking FPGA Code Is Arduino C++

Custom FPGA logic is normally written in:

and synthesised into hardware.

It does not execute line-by-line like a sketch.

Common Mistake 2: Treating 8 MB SDRAM as SAMD21 RAM

The SAMD21 still has only:

The 8 MB memory is part of the FPGA-oriented subsystem.

Common Mistake 3: Driving Shared Pins from Both Devices

Always decide whether the:

owns each output.

Common Mistake 4: Ignoring Timing Reports

FPGA designs must meet timing.

A successful compile is not the same as:

Common Mistake 5: Starting with HDMI

Video is one of the more complex FPGA workloads.

Start with:

• LED output;
• counter;
• simple register interface;
• PWM;
• UART;

before moving to video pipelines.

Common Mistake 6: Assuming Mini PCIe Means PCIe

The connector gives programmable FPGA pins in that mechanical format.

It does not automatically provide a standard PCIe endpoint.

Common Mistake 7: Ignoring EOL Status

For learning, Vidor remains interesting.

For a new commercial product, supply continuity and archived software repositories need to be part of the design decision.

Quick FPGA Reference

Recommended Learning Path

Final Thoughts

The MKR Vidor 4000 is not best understood as an Arduino with a mysterious “extra processor”.

It is:

The SAMD21 is suited to:

• Arduino libraries;
• USB;
• Wi-Fi control;
• application logic;
• configuration.

The FPGA is suited to:

• precise timing;
• parallel I/O;
• custom serial interfaces;
• high-resolution PWM;
• DSP;
• camera capture;
• HDMI/video pipelines.

The most important rule is to design a clear boundary between the two devices:

Once that architecture is clear, the Vidor becomes much easier to understand.

For the complete physical pin mapping, see our Arduino MKR Vidor 4000 pinout guide. For the rest of the family, see Arduino MKR boards compared.