The Arduino MKR Vidor 4000 is unlike almost every other board in the MKR family because it combines a normal Arduino microcontroller with a substantial FPGA.
The board contains:
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 |
SAMD21G18A → 48 MHz Arm Cortex-M0+ → normal Arduino sketch → GPIO, ADC, DAC, timers, USB and serial buses Intel Cyclone 10CL016 → FPGA fabric → custom digital hardware → high-speed I/O → video / signal processing → user-defined peripherals u-blox NINA-W102 → Wi-Fi → Bluetooth ATECC508A → hardware security |
Arduino now marks the MKR Vidor 4000 as End of Life, but it remains an unusual and capable board for existing projects and FPGA experimentation.
Quick MKR Vidor 4000 Specifications
| Feature | MKR Vidor 4000 |
|---|---|
| Main MCU | SAMD21G18A Cortex-M0+ |
| MCU clock | 48 MHz |
| MCU Flash | 256 KB |
| MCU SRAM | 32 KB |
| Logic voltage | 3.3 V |
| Analog inputs | 7, A0-A6 |
| ADC | 8/10/12-bit selectable |
| True DAC | 1 × 10-bit on A0 |
| PWM from SAMD21 | 13 documented pins |
| FPGA | Intel Cyclone 10CL016 |
| FPGA logic elements | 16K |
| FPGA embedded RAM | 504 kB |
| FPGA DSP multipliers | 56 × 18×18-bit |
| External FPGA SDRAM | 8 MB |
| FPGA configuration Flash | 2 MB QSPI, with 1 MB allocated for user applications |
| FPGA header I/O | 22 MKR-header pins |
| Additional FPGA I/O | 25 programmable Mini PCIe connector pins |
| Video output | Micro HDMI |
| Camera | MIPI camera connector |
| Wireless | NINA-W102 Wi-Fi / Bluetooth |
| Secure element | ATECC508A |
| USB | Micro-USB / native SAMD21 USB |
| Battery | 3.7 V single-cell Li-Po |
The Most Important Concept: Two Programmable Devices
Most Arduino boards have one processor controlling the external pins.
Vidor has:
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1 2 3 4 5 6 |
SAMD21 + FPGA |
and the board routes the MKR-format I/O so the FPGA can participate in external pin functions as well.
This means a pin can be used as a conventional Arduino GPIO under SAMD21 control or as part of FPGA logic, depending on the design.
Do Not Drive the Same Pin from Both Sides
A shared pin must have one clear owner.
Do not configure:
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1 2 3 4 5 6 7 8 |
SAMD21 → output HIGH FPGA → output LOW |
on the same physical signal.
That creates electrical contention.
When moving a function into the FPGA, make sure the SAMD21 side is placed in a compatible high-impedance/input state unless the design intentionally requires otherwise.
3.3 V Logic
Both the microcontroller and FPGA side operate in a:
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1 2 3 4 |
3.3 V I/O domain |
Do not treat MKR Vidor as a 5 V Arduino.
External:
- SPI;
- I2C;
- UART;
- parallel buses;
- analogue inputs;
must stay within the appropriate 3.3 V limits.
SAMD21 GPIO Current
Arduino’s current datasheet specifies:
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1 2 3 4 5 |
7 mA maximum per SAMD21 I/O pin |
with group-level current limits as well.
Use external drivers for:
- relays;
- motors;
- solenoids;
- high-current LEDs.
FPGA Output Current Is Configuration-Dependent
Do not assume FPGA pins are high-current outputs.
The allowed output current depends on the selected:
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1 2 3 4 5 6 |
I/O standard drive-strength setting FPGA bank configuration |
Arduino’s current Vidor datasheet summarises FPGA I/O current as:
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1 2 3 4 |
4 or 8 mA |
depending on configuration.
Check the FPGA I/O standard and Quartus constraints for any custom design.
Main MKR Header Pin Mapping
The SAMD21 side follows the familiar MKR layout:
| Arduino pin | SAMD21 pin | Main Arduino function |
|---|---|---|
| D0 | PA22 | GPIO / PWM |
| D1 | PA23 | GPIO / PWM |
| D2 | PA10 | GPIO / PWM |
| D3 | PA11 | GPIO / PWM |
| D4 | PB10 | GPIO / PWM |
| D5 | PB11 | GPIO / PWM |
| D6 | PA20 | GPIO / PWM |
| D7 | PA21 | GPIO / PWM |
| D8 | PA16 | GPIO / PWM / SPI COPI |
| D9 | PA17 | GPIO / SPI SCK |
| D10 | PA19 | GPIO / PWM / SPI CIPO |
| D11 | PA08 | GPIO / I2C SDA |
| D12 | PA09 | GPIO / PWM / I2C SCL |
| D13 | PB23 | GPIO / UART RX |
| D14 | PB22 | GPIO / UART TX |
Analog Inputs A0-A6
The board exposes:
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1 2 3 4 |
A0-A6 |
as analogue inputs.
They also have digital aliases:
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1 2 3 4 5 6 7 8 9 10 |
A0 = D15 A1 = D16 A2 = D17 A3 = D18 A4 = D19 A5 = D20 A6 = D21 |
| Analog pin | Digital alias | SAMD21 pin | Main function |
|---|---|---|---|
| A0 | D15 | PA02 | AIN0 / DAC0 |
| A1 | D16 | PB02 | AIN10 |
| A2 | D17 | PB03 | AIN11 |
| A3 | D18 | PA04 | AIN4 / PWM |
| A4 | D19 | PA05 | AIN5 / PWM |
| A5 | D20 | PA06 | AIN6 |
| A6 | D21 | PA07 | AIN7 |
ADC Resolution
Arduino supports:
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1 2 3 4 5 6 |
8-bit 10-bit 12-bit |
ADC modes on the SAMD21.
For full 12-bit Arduino reads:
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1 2 3 4 |
analogReadResolution(12); |
Then:
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1 2 3 4 |
analogRead(A1) |
returns approximately:
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1 2 3 4 |
0-4095 |
A0 Is a True DAC Output
A0 is connected to:
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1 2 3 4 |
DAC0 |
and provides a genuine:
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1 2 3 4 |
10-bit analogue output |
from the SAMD21.
DAC Example
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1 2 3 4 5 6 7 8 9 10 |
void setup() { analogWriteResolution(10); } void loop() { analogWrite(A0, 512); } |
SAMD21 PWM Pins
Arduino documents PWM on:
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 |
D0 D1 D2 D3 D4 D5 D6 D7 D8 D10 D12 A3 / D18 A4 / D19 |
for:
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1 2 3 4 |
13 PWM-capable pins |
under the normal SAMD21 Arduino core.
FPGA PWM Is Far More Flexible
The Cyclone 10 can synthesise custom PWM logic on FPGA-routed I/O.
Arduino’s datasheet describes all FPGA pins as configurable for functions such as:
- PWM;
- UART;
- SPI/QSPI;
- I2C;
- I2S;
- quadrature encoders;
- Sigma-Delta DAC;
- custom digital protocols.
This is not the same as calling:
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1 2 3 4 |
analogWrite() |
on every pin.
The FPGA function has to exist in the loaded FPGA design.
Hardware UART
The normal SAMD21 UART is:
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1 2 3 4 5 6 7 8 9 10 |
D13 → RX → PB23 D14 → TX → PB22 |
Use:
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1 2 3 4 |
Serial1 |
USB Serial
Because SAMD21 provides native USB:
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1 2 3 4 5 6 7 8 |
Serial → USB CDC Serial1 → D13/D14 UART |
so PC debugging does not consume the external UART.
I2C
The normal Arduino I2C bus is:
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1 2 3 4 5 6 7 8 9 10 |
D11 → SDA → PA08 D12 → SCL → PA09 |
Use:
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1 2 3 4 |
#include <Wire.h> |
SPI
The main SAMD21 SPI interface is:
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
D8 → COPI / MOSI → PA16 D9 → SCK → PA17 D10 → CIPO / MISO → PA19 |
Use:
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1 2 3 4 |
#include <SPI.h> |
FPGA Can Implement Additional Serial Buses
The FPGA is not limited to the SAMD21’s peripheral count.
Arduino’s datasheet states that, depending on the loaded FPGA configuration, it can implement up to:
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1 2 3 4 5 6 |
7 UARTs 7 SPI interfaces 7 I2C interfaces |
These are soft peripherals created in programmable logic.
Cyclone 10CL016 FPGA
The Vidor’s FPGA contains approximately:
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1 2 3 4 5 6 |
16K logic elements 504 kB embedded RAM 56 hardware 18×18 multipliers |
This gives the board hardware resources for:
- parallel processing;
- custom protocol engines;
- high-speed counters;
- DSP;
- video pipelines;
- precise timing.
FPGA I/O Can Toggle Much Faster Than MCU GPIO
Arduino states that FPGA pins can toggle at:
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1 2 3 4 |
over 150 MHz |
depending on design and timing constraints.
This is fundamentally different from bit-banging GPIO in a normal Arduino loop.
FPGA Clocking
The FPGA system runs from:
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1 2 3 4 |
48 MHz |
and internal PLLs can generate higher clocks, with Arduino documenting operation up to roughly:
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1 2 3 4 |
200 MHz |
for FPGA logic.
8 MB External SDRAM
The Vidor includes:
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1 2 3 4 |
8 MB SDRAM |
for FPGA workloads such as:
- video framebuffers;
- image processing;
- audio buffers;
- large streaming pipelines.
This memory is associated with the FPGA subsystem and should not be confused with the SAMD21’s:
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1 2 3 4 |
32 KB SRAM |
2 MB FPGA QSPI Flash
The FPGA subsystem also has:
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1 2 3 4 |
2 MB QSPI Flash |
for FPGA code/configuration.
Arduino states that approximately:
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1 2 3 4 |
1 MB |
is allocated for user FPGA applications.
Micro HDMI Output
The board includes a:
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1 2 3 4 |
Micro HDMI connector |
connected to the FPGA subsystem.
This enables FPGA-generated:
- graphics;
- video;
- test patterns;
- text displays;
- custom visualisation.
The connector should not be confused with DisplayPort: Vidor uses Micro HDMI.
MIPI Camera Connector
The board also has a:
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1 2 3 4 |
MIPI camera connector |
allowing image data to be routed into FPGA logic.
This supports projects such as:
- camera capture;
- QR-code processing;
- machine vision experiments;
- video filtering;
- real-time image pipelines.
Camera and HDMI Make Sense Because of the FPGA
The useful architecture is:
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1 2 3 4 5 6 7 8 |
MIPI camera → FPGA → image/video processing → SDRAM framebuffer → Micro HDMI |
A 48 MHz Cortex-M0+ on its own would not be the natural processor for that workload.
Mini PCIe-Style Connector
The bottom edge includes a:
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1 2 3 4 |
Mini PCI Express form-factor connector |
with up to:
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1 2 3 4 |
25 user-programmable FPGA pins |
plus power, ground and additional board signals.
Do Not Assume It Is a Normal PC PCIe Card
The connector uses the Mini PCIe mechanical format, but the exposed pins are primarily programmable FPGA I/O.
A standard PCIe interface does not magically appear merely because the connector has that shape.
The required protocol logic and electrical design must be implemented appropriately.
NINA-W102 Wireless Module
Wireless connectivity comes from:
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1 2 3 4 |
u-blox NINA-W102 |
which provides:
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1 2 3 4 5 6 |
2.4 GHz Wi-Fi 802.11 b/g/n Bluetooth Bluetooth Low Energy |
The NINA Module Is a Co-Processor
In normal Arduino use:
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1 2 3 4 5 6 7 8 |
SAMD21 → runs your sketch NINA-W102 → provides wireless networking |
The NINA module contains its own processor and memory, but it is not simply extra SAMD21 application RAM.
ATECC508A Secure Element
The board includes:
|
1 2 3 4 |
ATECC508A |
for hardware-assisted:
- key storage;
- device identity;
- SHA-256/HMAC operations;
- elliptic-curve cryptography;
- secure cloud authentication.
RGB LED
Vidor includes an onboard:
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1 2 3 4 |
RGB LED |
in addition to the normal MKR user-LED functionality.
Its exact control path depends on the board support/FPGA design being used.
Native USB
The SAMD21 provides native:
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1 2 3 4 |
Full-Speed USB |
through the board’s:
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1 2 3 4 |
Micro-USB |
connector.
This supports programming, USB serial and compatible native USB device functions.
Li-Po Battery Support
The board supports a:
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1 2 3 4 |
3.7 V single-cell Li-Po |
through its JST connector.
Arduino’s current datasheet specifies a recommended minimum battery capacity of:
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1 2 3 4 |
1024 mAh |
Power Input
The detailed current Arduino power section states that VIN should be a regulated supply in approximately the:
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1 2 3 4 |
5-6 V |
range.
Do not treat MKR Vidor VIN like the wide-range VIN input of a classic UNO or Mega.
5 V and 3.3 V Rails
The board provides:
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1 2 3 4 5 6 |
5 V 3.3 V GND |
power connections.
The 5 V rail is a power rail only.
External logic should still be designed around:
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1 2 3 4 |
3.3 V I/O |
Programming the FPGA
There are two broad approaches:
Arduino FPGA Libraries / Prebuilt Bitstreams
For supported Arduino examples, a prebuilt FPGA design can expose functions to the SAMD21 sketch.
Intel Quartus Prime
For custom hardware logic, Arduino’s documentation points to:
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1 2 3 4 |
Intel Quartus Prime |
for HDL design, synthesis and FPGA programming workflows.
The FPGA Is Not Just a Faster Microcontroller
This distinction matters.
A microcontroller executes instructions:
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1 2 3 4 5 6 |
instruction → instruction → instruction |
An FPGA implements hardware logic that can run many functions simultaneously:
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1 2 3 4 5 6 7 8 9 10 11 12 |
counter + PWM engine + UART + video pipeline + encoder decoder |
all operating in parallel.
Common Mistake 1: Applying 5 V to GPIO
The board is a:
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1 2 3 4 |
3.3 V logic platform |
Use level shifting for incompatible 5 V peripherals.
Common Mistake 2: Treating FPGA Pins as High-Current GPIO
FPGA drive strength depends on configuration.
Use external drivers for loads and observe the selected FPGA I/O standard.
Common Mistake 3: Driving a Pin from SAMD21 and FPGA Simultaneously
Give every shared physical signal one clear output owner.
Otherwise the devices can electrically fight each other.
Common Mistake 4: Assuming Every Pin Automatically Has FPGA PWM
The FPGA can implement PWM on many pins, but only if the loaded FPGA design contains the required PWM logic and routing.
Common Mistake 5: Calling the Video Port Mini DisplayPort
The official board provides:
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1 2 3 4 |
Micro HDMI |
not Mini DisplayPort.
Common Mistake 6: Assuming Mini PCIe Means Plug-and-Play PCIe
The connector primarily exposes FPGA-programmable signals in that mechanical format.
The FPGA design must implement whatever digital interface the application needs.
Common Mistake 7: Treating FPGA SDRAM as SAMD21 RAM
The SAMD21 still has:
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1 2 3 4 |
32 KB SRAM |
while the:
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1 2 3 4 |
8 MB SDRAM |
belongs to the FPGA-oriented memory subsystem.
Common Mistake 8: Starting a New Product Without Noticing EOL Status
Arduino currently marks the MKR Vidor 4000:
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1 2 3 4 |
End of Life |
It remains useful for existing hardware and learning, but long-term availability should be considered before using it in a new production design.
Quick SAMD21 Pin Reference
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 |
D0 PA22 PWM D1 PA23 PWM D2 PA10 PWM D3 PA11 PWM D4 PB10 PWM D5 PB11 PWM D6 PA20 PWM D7 PA21 PWM D8 PA16 PWM / COPI D9 PA17 SCK D10 PA19 PWM / CIPO D11 PA08 SDA D12 PA09 PWM / SCL D13 PB23 RX D14 PB22 TX |
Quick Analog Reference
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 |
A0 / D15 PA02 AIN0 DAC0 A1 / D16 PB02 AIN10 A2 / D17 PB03 AIN11 A3 / D18 PA04 AIN4 PWM A4 / D19 PA05 AIN5 PWM A5 / D20 PA06 AIN6 A6 / D21 PA07 AIN7 |
Quick Interface Reference
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 |
USB serial: Serial Hardware UART: D13 RX D14 TX Serial1 I2C: D11 SDA D12 SCL SPI: D8 COPI D9 SCK D10 CIPO FPGA: Cyclone 10CL016 16K logic elements 504 kB embedded RAM 56 DSP multipliers 8 MB external SDRAM 2 MB QSPI Flash 22 MKR header I/O 25 Mini PCIe programmable pins Video: Micro HDMI Camera: MIPI Wireless: NINA-W102 Wi-Fi / Bluetooth |
Final Thoughts
The MKR Vidor 4000 is best understood as:
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1 2 3 4 5 6 |
a SAMD21 Arduino + a Cyclone 10 FPGA development platform |
The SAMD21 side gives familiar Arduino features:
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1 2 3 4 5 6 7 8 9 10 11 |
ADC DAC PWM UART SPI I2C USB Wi-Fi control |
while the FPGA side adds:
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1 2 3 4 5 6 7 8 9 10 |
parallel hardware high-speed I/O custom peripherals DSP camera processing video output programmable Mini PCIe pins |
The most important pinout rules are:
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 |
logic voltage → 3.3 V SAMD GPIO current → 7 mA maximum UART → D13/D14 I2C → D11/D12 SPI → D8/D9/D10 ADC → A0-A6 DAC → A0 video → Micro HDMI camera → MIPI shared pins → avoid SAMD21/FPGA output contention |
For conventional SAMD21 MKR boards, see our MKR WiFi 1010 pinout guide, MKR Zero pinout guide and MKR WAN 1310 pinout guide.